Many integrated circuit memories, including DRAMs and DRAM macros embedded in logic integrated circuits (ICs), include column redundancies as available replacements for defective elements that lie anywhere along a column path from a memory array to a data bus. Thus, if a column fails for any reason, a test and repair procedure is used to replace the defective column with a column redundancy.
Column redundancies thus represent an excess in the number of available column data paths to a memory array over the number of data bits carried by an input/output data bus during normal operation. Since column redundancies are used in normal operation only if columns are determined to be defective, it is undesirable to provide complete parallel data paths for the redundancies to the exterior of the IC memory (such as to separate pins), or to the exterior of a memory macro, because of the additional IC area and external pins required.
At production test time for the IC memory or memory macro, it is necessary to test each of the columns of the memory array as well as the column redundancies to determine the existence of any defects therein. However, up to now, unless complete parallel data paths were provided from the memory array to the exterior of the IC or memory macro for these column redundancies, the column redundancies could not be tested in the same test pass as the regular columns of the memory array. Moreover, each test pass took significant time to complete because column operation had to be tested by individually cycling each wordline of the memory array on and off in sequence until the entire wordline space had been tested.
It would therefore be desirable to provide a way to test column redundancies in the same test pass of the memory array as regular columns, but without needing to provide separate complete data paths from memory array to the exterior. In this way, significant test time is saved without requiring the external input/output data buses or pin count to be enlarged.